Ara mostrant els elements 277-296 de 368

    Power-constrained aware and latency-aware microarchitectural optimizations in many-core processors 

    Jha, Sudhanshu S. (Data de defensa: 2016-10-05)

    As the transistor budgets outpace the power envelope (the power-wall issue), new architectural and microarchitectural techniques are needed to improve, or at least maintain, the power efficiency of next-generation processors. ...

    Practical strategies to monitor and control contention in shared resources of critical real-time embedded systems 

    Cardona Nadal, Jordi (Data de defensa: 2023-04-03)

    (English) In the last decade performance needs in Critical Real-Time Embedded Systems (CRTES) domains like automotive, avionics, railway or space have been steadily on the rise due to the unprecedented computational power ...

    Predicated execution and register windows for out-of-order processors 

    Quiñones Moreno, Eduardo (Data de defensa: 2008-11-18)

    ISA extensions are a very powerful approach to implement new hardware techniques that require or benefit from compiler support: decisions made at compile time can be complemented at runtime, achieving a synergistic effect ...

    Priority realloc : a threefold mechanism for route and resources allocation in EONs 

    Dantas, Joana Sócrates (Data de defensa: 2015-07-17)

    Backbone networks are responsible for long-haul data transport serving many clients with a large volume of data. Since long-haul data transport service must rely on a robust high capacity network the current technology ...

    Proactive software rejuvenation solution for web enviroments on virtualized platforms 

    Alonso López, Javier (Data de defensa: 2011-02-21)

    The availability of the Information Technologies for everything, from everywhere, at all times is a growing requirement. We use information Technologies from common and social tasks to critical tasks like managing nuclear ...

    Probabilistically time-analyzable complex processor designs 

    Slijepcevic, Mladen (Data de defensa: 2017-11-13)

    Industry developing Critical Real-Time Embedded Systems (CRTES), such as Aerospace, Space, Automotive and Railways, faces relentless demands for increased guaranteed processor performance to support new advanced functionalities ...

    Programming and parallelising applications for distributed infrastructures 

    Tejedor Saavedra, Enric (Data de defensa: 2013-07-15)

    The last decade has witnessed unprecedented changes in parallel and distributed infrastructures. Due to the diminished gains in processor performance from increasing clock frequency, manufacturers have moved from uniprocessor ...

    Programming model abstractions for optimizing I/O intensive applications 

    Elshazly, Hatem Mohamed Abdelfattah Eid (Data de defensa: 2022-01-28)

    This thesis contributes from the perspective of task-based programming models to the efforts of optimizing I/O intensive applications. Throughout this thesis, we propose programming model abstractions and mechanisms that ...

    Programming models and scheduling techniques for heterogeneous architectures 

    Planas Carbonell, Judit (Data de defensa: 2015-11-03)

    There is a clear trend nowadays to use heterogeneous high-performance computers, as they offer considerably greater computing power than homogeneous CPU systems. Extending traditional CPU systems with specialized units ...

    Programming models for mobile environments 

    Lordan Gomis, Francesc-Josep (Data de defensa: 2018-07-20)

    For the last decade, mobile devices have grown in popularity and became the best-selling computing devices. Despite their high capabilities for user interactions and network connectivity, the computing power of mobile ...

    Programming models to support data science workflows 

    Ramón-Cortés Vilarrodona, Cristián (Data de defensa: 2020-09-21)

    Data Science workflows have become a must to progress in many scientific areas such as life, health, and earth sciences. In contrast to traditional HPC workflows, they are more heterogeneous; combining binary executions, ...

    Programming, debugging, profiling and optimizing transactional memory programs 

    Hasanov Zyulkyarov, Ferard (Data de defensa: 2011-07-19)

    Transactional memory (TM) is a new optimistic synchronization technique which has the potential of making shared memory parallel programming easier compared to locks without giving up from the performance. This thesis ...

    Protocolo activo para transmisiones garantizadas sobre una arquitectura distribuída y multiagente en redes ATM 

    González Sánchez, José Luís (Data de defensa: 2001-07-24)

    En esta tesis doctoral se presenta TAP (Trusted and Active Protocol PDU transfer), una arquitectura para redes de tecnología ATM, novedosa por sus características distribuida, activa y multiagente. El protocolo propuesto ...

    Proveïment de QoS en xarxes de paquets òptiques per a entorns d'àrea metropolitana i de gran abast 

    Careglio, Davide (Data de defensa: 2005-02-15)

    El gran crecimiento y expansión de Internet en los últimos años, con el consecuente incremento de usuarios y tráfico, ha hecho que aumente la necesidad de ancho de banda en las redes de telecomunicación actuales. El desafío ...

    Quality of service on ad-hoc wireless networks 

    Paoliello Guimaraes, Rafael (Data de defensa: 2008-07-14)

    Over the last years, Mobile Ad-hoc Networks (MANETs) have captured the attention of the research community. The flexibility and cost savings they provide, due to the fact that no infrastructure is needed to deploy a MANET, ...

    Query expansion by relying on the structure of knowledge bases 

    Guisado Gámez, Joan (Data de defensa: 2017-09-28)

    Query expansion techniques aim at improving the results achieved by a user's query by means of introducing new expansion terms, called expansion features. Expansion features introduce new concepts that are semantically ...

    Raising the level of abstraction : simulation of large chip multiprocessors running multithreaded applications 

    Rico Carro, Alejandro (Data de defensa: 2013-10-29)

    The number of transistors on an integrated circuit keeps doubling every two years. This increasing number of transistors is used to integrate more processing cores on the same chip. However, due to power density and ILP ...

    Real-time high-performance computing for embedded control systems 

    Calderón Torres, Alejandro Josué (Data de defensa: 2022-07-21)

    The real-time control systems industry is moving towards the consolidation of multiple computing systems into fewer and more powerful ones, aiming for a reduction in size, weight, and power. The increasing demand for higher ...

    Recursos anchos: una técnica de bajo coste para explotar paralelismo agresivo en códigos numéricos 

    López Álvarez, David (Data de defensa: 1998-12-15)

    Els bucles son la part que més temps consumeix en les aplicacions numèriques. El rendiment dels bucles està limitat tant pels recursos oferts per l'arquitectura com per les recurrències del bucle en la computació. ...

    Reducing redundancy of real time computer graphics in mobile systems 

    De Lucas, Enrique (Data de defensa: 2018-04-20)

    The goal of this thesis is to propose novel and effective techniques to eliminate redundant computations that waste energy and are performed in real-time computer graphics applications, with special focus on mobile GPU ...