Programa de Doctorat en Arquitectura de Computadors: Recent submissions
Now showing items 261-272 of 272
Architectural explorations for streaming accelerators with customized memory layouts
El concepto básico de la arquitectura mono-nucleo en los procesadores de propósito general se ajusta bien a un modelo de programación secuencial. La integración de multiples núcleos en un solo chip ha permitido a los ...
Cross-layer optimization in optical networks
Network planning and operation in core optical networks require processes that lead to a cost-effective network able to effectively accommodate the given traffic demands. Crosslayer techniques that exploit information ...
Opportunistic routing in wireless mesh networks
Advances in communication and networking technologies are rapidly making ubiquitous network connectivity a reality. In recent years, Wireless Mesh Networks (WMNs) have already become very popular and been receiving an ...
Software caching techniques and hardware optimizations for on-chip local memories
Despite the fact that the most viable L1 memories in processors are caches, on-chip local memories have been a great topic of consideration lately. Local memories are an interesting design option due to their many benefits: ...
Efficient algorithms for passive network measurement
Network monitoring has become a necessity to aid in the management and operation of large networks. Passive network monitoring consists of extracting metrics (or any information of interest) by analyzing the traffic that ...
Adaptive memory hierarchies for next generation tiled microarchitectures
Les últimes dècades el rendiment dels processadors i de les memòries ha millorat a diferent ritme, limitant el rendiment dels processadors i creant el conegut memory gap. Sol·lucionar aquesta diferència de rendiment és un ...
Multifaceted resource management on virtualized providers
Last decade, providers started using Virtual Machines (VMs) in their datacenters to pack users and their applications. This was a good way to consolidate multiple users in fewer physical nodes while isolating them from ...
Architectural support for high-performing hardware transactional memory systems
Parallel programming presents an efficient solution to exploit future multicore processors. Unfortunately, traditional programming models depend on programmer’s skills for synchronizing concurrent threads, which makes ...
Managing dynamic non-uiform cache architectures
Researchers from both academia and industry agree that future CMPs will accommodate large shared on-chip last-level caches. However, the exponential increase in multicore processor cache sizes accompanied by growing on-chip ...
GMPLS-OBS interoperability and routing acalability in internet
The popularization of Internet has turned the telecom world upside down over the last two decades. Network operators, vendors and service providers are being challenged to adapt themselves to Internet requirements in a way ...
A Multi-core processor for hard real-time systems
The increasing demand for new functionalities in current and future hard real-time embedded systems, like the ones deployed in automotive and avionics industries, is driving an increment in the performance required in ...
Programming, debugging, profiling and optimizing transactional memory programs
Transactional memory (TM) is a new optimistic synchronization technique which has the potential of making shared memory parallel programming easier compared to locks without giving up from the performance. This thesis ...
