Programa de Doctorat en Arquitectura de Computadors: Enviaments recents
Ara mostrant els elements 161-180 de 272
On algorithmic reductions in task-parallel programming models
Wide adoption of parallel processing hardware in mainstream computing as well as the interest for efficient parallel programming in developer communities increase the demand for programming models that offer support for ...
Dynamic load balancing for hybrid applications
It is well known that load imbalance is a major source of efficiency loss in HPC (High Performance Computing) environments. The load imbalance problem has very different sources, from static ones related to the data ...
dataClay : next generation object storage
Existing solutions for data sharing are not fully compatible with multi-provider contexts. Traditionally, providers offer their datasets through hermetic Data Services with restricted APIs. Therefore, consumers are compelled ...
Towards multiprogrammed GPUs
Programmable Graphics Processing Units (GPUs) have recently become the most pervasitheve massively parallel processors. They have come a long way, from fixed function ASICs designed to accelerate graphics tasks to a ...
Design of energy-efficient vector units for in-order cores
In the last 15 years, power dissipation and energy consumption have become crucial design concerns for almost all computer systems. Technology feature size scaling leads to higher power density and therefore to complex and ...
On the design of power- and energy-efficient functional units for vector processors
Vector processors are a very promising solution for mobile devices and servers due to their inherently energy-efficient way of exploiting datalevel parallelism. While vector processors succeeded in the high performance ...
Improving prefetching mechanisms for tiled CMP platforms
Recently, high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures to deal with instruction level parallelism limitations and, more important, to manage the power consumption that is ...
Performance-aware energy optimizations in networks for HPC
Energy efficiency is an important challenge in the field of High Performance Computing (HPC). High energy requirements not only limit the potential to realize next-generation machines but are also an increasing part of the ...
Improving the efficiency of multicore systems through software and hardware cooperation
Increasing processors' clock frequency has traditionally been one of the largest drivers of performance improvements for computing systems. In the first half of the 2000s, however, it became clear that continuing to increase ...
Power-constrained aware and latency-aware microarchitectural optimizations in many-core processors
As the transistor budgets outpace the power envelope (the power-wall issue), new architectural and microarchitectural techniques are needed to improve, or at least maintain, the power efficiency of next-generation processors. ...
A multicore emulator with a profiling Infrastructure for transactional memory on FPGA
This thesis attempts to bring together two recent topics by presenting a flexible Transactional Memory environment on a multicore prototype that is realized on FPGA fabric. For this, we devise a MIPS-compatible shared-memory ...
Decoupling state from control in software-defined networking
Software-Defined Networking (SDN) arose as a solution to address the limitations of traditional networking. In SDN networks, the control-plane is decoupled from the data-plane devices and logically centralized in a new ...
Soft error mitigation techniques for future chip multiprocessors
The sustained drive to downsize the transistors has reached a point where device sensitivity against transient faults due to neutron and alpha particle strikes a.k.a soft errors has moved to the forefront of concerns for ...
The MPI/OmpSs parallel programming model
Even today supercomputing systems have already reached millions of cores for a single machine, which are connected by using a complex network interconnection. Reducing communication time across processes becomes the most ...
Reliability for exascale computing : system modelling and error mitigation for task-parallel HPC applications
As high performance computing (HPC) systems continue to grow, their fault rate increases. Applications running on these systems have to deal with rates on the order of hours or days. Furthermore, some studies for future ...
Improving time predictability of shared hardware resources in real-time multicore systems : emphasis on the space domain
Critical Real-Time Embedded Systems (CRTES) follow a verification and validation process on the timing and functional correctness. This process includes the timing analysis that provides Worst-Case Execution Time (WCET) ...
Novel vector architectures for data management
As the rate of annual data generation grows exponentially, there is a demand to manage, query and summarise vast amounts of information quickly. In the past, frequency scaling was relied upon to push application throughput. ...
Co-designed solutions for overhead removal in dynamically typed languages
Dynamically typed languages are ubiquitous in today's applications. These languages ease the task of programmers but introduce significant runtime overheads since variables are neither declared nor bound to a particular ...
Statistical analysis and design of subthreshold operation memories
This thesis presents novel methods based on a combination of well-known statistical techniques for faster estimation of memory yield and their application in the design of energy-efficient subthreshold memories. The emergence ...
Energy sharing in smart grids : a game theory approach
The need for energy conservation, grid reliability, and improved operational efficiencies have led to the changes from conventional electricity grids which have “blind” and manual operations, along with the electromechanical ...
