Programa de Doctorat en Arquitectura de Computadors: Envíos recientes
Mostrando ítems 241-260 de 260
Enhancing the efficiency and practicality of software transactional memory on massively multithreaded systems
Chip Multithreading (CMT) processors promise to deliver higher performance by running more than one stream of instructions in parallel. To exploit CMT's capabilities, programmers have to parallelize their applications, ...
Cross-layer modeling and optimization of next-generation internet networks
Scaling traditional telecommunication networks so that they are able to cope with the volume of future traffic demands and the stringent European Commission (EC) regulations on emissions would entail unaffordable investments. ...
Desarrollo de un workflow genérico para el modelado de problemas de barrido paramétrico en sistemas distribuidos
This work presents the development and experimental validation of a generic workflow model applicable to any parameter sweep problem: the Parameter Sweep Scientific Workflow (PSWF) model. As part of it, a model for the ...
Distributed detection of anomalous internet sessions
Financial service providers are moving many services online reducing their costs and facilitating customers¿ interaction. Unfortunately criminals have quickly found several ways to avoid most security measures applied to ...
Channel assignment protocols for multi-radio multi-channel wireless mesh netwworks
The increasing demand for large and low cost wireless coverage, ranging from campus to city wide areas, has motivated a high interest in multi-hop communications with Wireless Mesh Networks (WMN) based on IEEE 802.11s as ...
Characterization, design and re-optimization on multi-layer optical networks
L'augment de volum de tràfic IP provocat per l'increment de serveis multimèdia com HDTV o vídeo conferència planteja nous reptes als operadors de xarxa per tal de proveir transmissió de dades eficient. Tot i que les xarxes ...
An Online writer recognition system based on in-air and on-surface trajectories
The main motivation of this dissertation is the exploration of the field of online text-dependent writer recognition, in order to provide evidence of the usefulness of short sequences of text to perform identification and ...
DVFS power management in HPC systems
Recent increase in performance of High Performance Computing (HPC) systems has been followed by even higher increase in power consumption. Power draw of modern supercomputers leads to very high operating costs and ...
Architectural explorations for streaming accelerators with customized memory layouts
El concepto básico de la arquitectura mono-nucleo en los procesadores de propósito general se ajusta bien a un modelo de programación secuencial. La integración de multiples núcleos en un solo chip ha permitido a los ...
Cross-layer optimization in optical networks
Network planning and operation in core optical networks require processes that lead to a cost-effective network able to effectively accommodate the given traffic demands. Crosslayer techniques that exploit information ...
Opportunistic routing in wireless mesh networks
Advances in communication and networking technologies are rapidly making ubiquitous network connectivity a reality. In recent years, Wireless Mesh Networks (WMNs) have already become very popular and been receiving an ...
Software caching techniques and hardware optimizations for on-chip local memories
Despite the fact that the most viable L1 memories in processors are caches, on-chip local memories have been a great topic of consideration lately. Local memories are an interesting design option due to their many benefits: ...
Efficient algorithms for passive network measurement
Network monitoring has become a necessity to aid in the management and operation of large networks. Passive network monitoring consists of extracting metrics (or any information of interest) by analyzing the traffic that ...
Adaptive memory hierarchies for next generation tiled microarchitectures
Les últimes dècades el rendiment dels processadors i de les memòries ha millorat a diferent ritme, limitant el rendiment dels processadors i creant el conegut memory gap. Sol·lucionar aquesta diferència de rendiment és un ...
Multifaceted resource management on virtualized providers
Last decade, providers started using Virtual Machines (VMs) in their datacenters to pack users and their applications. This was a good way to consolidate multiple users in fewer physical nodes while isolating them from ...
Architectural support for high-performing hardware transactional memory systems
Parallel programming presents an efficient solution to exploit future multicore processors. Unfortunately, traditional programming models depend on programmer’s skills for synchronizing concurrent threads, which makes ...
Managing dynamic non-uiform cache architectures
Researchers from both academia and industry agree that future CMPs will accommodate large shared on-chip last-level caches. However, the exponential increase in multicore processor cache sizes accompanied by growing on-chip ...
GMPLS-OBS interoperability and routing acalability in internet
The popularization of Internet has turned the telecom world upside down over the last two decades. Network operators, vendors and service providers are being challenged to adapt themselves to Internet requirements in a way ...
A Multi-core processor for hard real-time systems
The increasing demand for new functionalities in current and future hard real-time embedded systems, like the ones deployed in automotive and avionics industries, is driving an increment in the performance required in ...
Programming, debugging, profiling and optimizing transactional memory programs
Transactional memory (TM) is a new optimistic synchronization technique which has the potential of making shared memory parallel programming easier compared to locks without giving up from the performance. This thesis ...
