Departament d'Arquitectura de Computadors: Envíos recientes
Mostrando ítems 141-160 de 364
Resource, data and application management for cloud federations and multi-clouds
Distributed Real-Time Media Processing refers to classes of highly distributed, delay no-tolerant applications that account for the majority of the data traffic generated in the world today. Real-Time audio/video conferencing ...
On the service placement in community network micro-clouds
Community networks (CNs) have gained momentum in the last few years in response to the growing demand for network connectivity in rural and urban areas. These networks, owned and managed by volunteers, offer various services ...
Internet sharing in community networks
The majority of the world's population does not have any or adequate Internet access. This implies that the Internet cannot provide universal service, reaching everyone without discrimination. Global access to the Internet ...
Dynamic load balancing for hybrid applications
It is well known that load imbalance is a major source of efficiency loss in HPC (High Performance Computing) environments. The load imbalance problem has very different sources, from static ones related to the data ...
dataClay : next generation object storage
Existing solutions for data sharing are not fully compatible with multi-provider contexts. Traditionally, providers offer their datasets through hermetic Data Services with restricted APIs. Therefore, consumers are compelled ...
Towards multiprogrammed GPUs
Programmable Graphics Processing Units (GPUs) have recently become the most pervasitheve massively parallel processors. They have come a long way, from fixed function ASICs designed to accelerate graphics tasks to a ...
Design of energy-efficient vector units for in-order cores
In the last 15 years, power dissipation and energy consumption have become crucial design concerns for almost all computer systems. Technology feature size scaling leads to higher power density and therefore to complex and ...
On the design of power- and energy-efficient functional units for vector processors
Vector processors are a very promising solution for mobile devices and servers due to their inherently energy-efficient way of exploiting datalevel parallelism. While vector processors succeeded in the high performance ...
Improving prefetching mechanisms for tiled CMP platforms
Recently, high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures to deal with instruction level parallelism limitations and, more important, to manage the power consumption that is ...
Performance-aware energy optimizations in networks for HPC
Energy efficiency is an important challenge in the field of High Performance Computing (HPC). High energy requirements not only limit the potential to realize next-generation machines but are also an increasing part of the ...
On the role of performance interference in consolidated environments
With the advent of resource shared environments such as the Cloud, virtualization has become the de facto standard for server consolidation. While consolidation improves utilization, it causes performance-interference ...
Improving the efficiency of multicore systems through software and hardware cooperation
Increasing processors' clock frequency has traditionally been one of the largest drivers of performance improvements for computing systems. In the first half of the 2000s, however, it became clear that continuing to increase ...
Power-constrained aware and latency-aware microarchitectural optimizations in many-core processors
As the transistor budgets outpace the power envelope (the power-wall issue), new architectural and microarchitectural techniques are needed to improve, or at least maintain, the power efficiency of next-generation processors. ...
A multicore emulator with a profiling Infrastructure for transactional memory on FPGA
This thesis attempts to bring together two recent topics by presenting a flexible Transactional Memory environment on a multicore prototype that is realized on FPGA fabric. For this, we devise a MIPS-compatible shared-memory ...
Decoupling state from control in software-defined networking
Software-Defined Networking (SDN) arose as a solution to address the limitations of traditional networking. In SDN networks, the control-plane is decoupled from the data-plane devices and logically centralized in a new ...
Soft error mitigation techniques for future chip multiprocessors
The sustained drive to downsize the transistors has reached a point where device sensitivity against transient faults due to neutron and alpha particle strikes a.k.a soft errors has moved to the forefront of concerns for ...
The MPI/OmpSs parallel programming model
Even today supercomputing systems have already reached millions of cores for a single machine, which are connected by using a complex network interconnection. Reducing communication time across processes becomes the most ...
Reliability for exascale computing : system modelling and error mitigation for task-parallel HPC applications
As high performance computing (HPC) systems continue to grow, their fault rate increases. Applications running on these systems have to deal with rates on the order of hours or days. Furthermore, some studies for future ...
Improving time predictability of shared hardware resources in real-time multicore systems : emphasis on the space domain
Critical Real-Time Embedded Systems (CRTES) follow a verification and validation process on the timing and functional correctness. This process includes the timing analysis that provides Worst-Case Execution Time (WCET) ...
Novel vector architectures for data management
As the rate of annual data generation grows exponentially, there is a demand to manage, query and summarise vast amounts of information quickly. In the past, frequency scaling was relied upon to push application throughput. ...
