Exploring coordinated software and hardware support for hardware resource allocation

dc.contributor
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.author
Figueiredo Boneti, Carlos Santieri de
dc.date.accessioned
2011-04-12T15:02:58Z
dc.date.available
2010-11-19
dc.date.issued
2009-09-04
dc.date.submitted
2010-11-18
dc.identifier.isbn
9788469404294
dc.identifier.uri
http://www.tdx.cat/TDX-1118110-122120
dc.identifier.uri
http://hdl.handle.net/10803/6018
dc.description.abstract
Multithreaded processors are now common in the industry as they offer high performance at a low cost. Traditionally, in such processors, the assignation of hardware resources between the multiple threads is done implicitly, by the hardware policies. However, a new class of multithreaded hardware allows the explicit allocation of resources to be controlled or biased by the software. Currently, there is little or no coordination between the allocation of resources done by the hardware and the prioritization of tasks done by the software.<br/>This thesis targets to narrow the gap between the software and the hardware, with respect to the hardware resource allocation, by proposing a new explicit resource allocation hardware mechanism and novel schedulers that use the currently available hardware resource allocation mechanisms.<br/>It approaches the problem in two different types of computing systems: on the high performance computing domain, we characterize the first processor to present a mechanism that allows the software to bias the allocation hardware resources, the IBM POWER5. In addition, we propose the use of hardware resource allocation as a way to balance high performance computing applications. Finally, we propose two new scheduling mechanisms that are able to transparently and successfully balance applications in real systems using the hardware resource allocation. On the soft real-time domain, we propose a hardware extension to the existing explicit resource allocation hardware and, in addition, two software schedulers that use the explicit allocation hardware to improve the schedulability of tasks in a soft real-time system.<br/>In this thesis, we demonstrate that system performance improves by making the software aware of the mechanisms to control the amount of resources given to each running thread. In particular, for the high performance computing domain, we show that it is possible to decrease the execution time of MPI applications biasing the hardware resource assignation between threads. In addition, we show that it is possible to decrease the number of missed deadlines when scheduling tasks in a soft real-time SMT system.
eng
dc.format.mimetype
application/pdf
dc.language.iso
eng
dc.publisher
Universitat Politècnica de Catalunya
dc.rights.license
ADVERTIMENT. L'accés als continguts d'aquesta tesi doctoral i la seva utilització ha de respectar els drets de la persona autora. Pot ser utilitzada per a consulta o estudi personal, així com en activitats o materials d'investigació i docència en els termes establerts a l'art. 32 del Text Refós de la Llei de Propietat Intel·lectual (RDL 1/1996). Per altres utilitzacions es requereix l'autorització prèvia i expressa de la persona autora. En qualsevol cas, en la utilització dels seus continguts caldrà indicar de forma clara el nom i cognoms de la persona autora i el títol de la tesi doctoral. No s'autoritza la seva reproducció o altres formes d'explotació efectuades amb finalitats de lucre ni la seva comunicació pública des d'un lloc aliè al servei TDX. Tampoc s'autoritza la presentació del seu contingut en una finestra o marc aliè a TDX (framing). Aquesta reserva de drets afecta tant als continguts de la tesi com als seus resums i índexs.
dc.source
TDX (Tesis Doctorals en Xarxa)
dc.subject
MT
dc.subject
CMP
dc.subject
harware priorities
dc.subject
thread prioritization
dc.subject
resource balancing
dc.subject
load balancing
dc.subject
powers
dc.subject
simultaneous multithreading
dc.subject
SMT
dc.subject
hardware-software codesign
dc.subject
performance characterization
dc.subject
software-controlled prioritization
dc.title
Exploring coordinated software and hardware support for hardware resource allocation
dc.type
info:eu-repo/semantics/doctoralThesis
dc.type
info:eu-repo/semantics/publishedVersion
dc.subject.udc
004
cat
dc.contributor.director
Cazorla Almeida, Francisco Javier
dc.contributor.codirector
Valero Cortés, Mateo
dc.contributor.codirector
Gioiosa, Roberto
dc.rights.accessLevel
info:eu-repo/semantics/openAccess
dc.identifier.dl
B.11716-2011


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