Low-power high-channel-count CMOS ROICs for multiplexed arrays of graphene transistors in large-area µECoG

Abstract

(English) There is an increasing interest on the development of neural interfaces able to decipher the neural activity across multiple regions of the brain. The ultimate goal is understanding how the underlying brain dynamics drive the cognitive activities, such learning and moving or the response towards impairing diseases. Despite the huge advance in neuroscience, there is still a lack of knowledge for a complete conception of the brain, mainly because the neural activity spans over a wide range of temporal and spatial resolutions making it difficult to be recorded with a single technology.

The electrical nature of the brain activity makes electrophysiology of paramount importance for the deep study of brain dynamics. Indeed, the current state-of-art invasive electrophysiological techniques include intracortical monolithic CMOS ROICs able to resolve the neural activity from single neurons, and epicortical hybrid MEAs for the recording of µECoG signals. The monolithic solutions have benefited from the scalability of CMOS technologies, with on-chip recording sensors and circuits, while hybrid neural interfaces still suffer from the point-to-point connectivity limitations and they have been mainly focused on exotic materials and discrete electronics.

This PhD thesis explores novel multiplexing techniques for graphene active sensing arrays by means of tailored ROIC architectures and mixed-signal CMOS circuits, which extend the state-of-art coverage to larger areas with high-density neural interfaces by solving the current connectivity restrictions of hybrid systems. In this sense, this research presents two 1024-channel ROIC demonstrators in 1.8-V 180-nm CMOS technology representing a substantial increment on the channel count in hybrid systems while keeping the system integration at low cost and low complexity.

The first research line, proposes a conservative approach based on a time-domain multiplexing scheme to minimize the connectivity for G-SGFET-only sensor arrays by moving the selection switches to the CMOS ROIC. Apart from solving the connectivity issue, the proposed multiplexing scheme is able to reduce the array technological complexity while preserving the demonstrated DC-coupled neural recording capability of G-SGFET sensors. Moreover, a modular ROIC architecture and accompanying CMOS circuits are introduced to overcome the main design challenges on channel-count scalability, like individual offset current cancellation or the degradation of the AFE noise figures. In addition, electrical tests together with in-vivo experimental results are presented to support the system capabilities of this first complete state-of-art hybrid ROIC specially designed for G-SGFET sensors.

The second research line proposes a novel frequency-domain multiplexing technique capable of exploiting the intrinsic mixer capabilities of the graphene transistor to achieve a truly switch-less operation of high-channel-count G-SGFET-only probes. The mixing process allocates in continuous time the desired neural signal from the gate of the sensor into a desired frequency band avoiding both CMOS flicker noise and sampled noise folding. Scalability in this state-of-art advancement is reached by means of a custom modular ROIC architecture and specific CMOS circuit blocks. Indeed, the solutions are presented for the main design challenges in terms of generation of the required harmonic carriers and optimization of the shared full scale occupancy. The resulting neural interface is still DC coupled and capable of infra-slow recording. Finally, electrical test and in-vivo experiments are reported to support the working hypothesis.